学位

• Bachelor of Science in Electronics - Telecommunications,(University of Science, Vietnam National University, Hochiminh city,)
• ()
• Master of Science in Electronic Engineering,(University of Science, Vietnam National University, Hochiminh city,)
• ()
• 博士（工学）、(国立大学法人　電気通信大学、)
• ()

経歴

学歴

受賞

その他

論文

• Efficient Hardware Implementation of the Lightweight CRYSTALS-Kyber [DOI] [Othres link]
• A True Random Number Generator on FPGA with Jitter-Sampling by Ring Generator [DOI] [Othres link]
• A Compact SHA3 Implementation for Post-Quantum Cryptography [DOI] [Othres link]
• Resource-Efficient 4×4 S-Boxes Using Chaotic Map [DOI] [Othres link]
• Hardware Implementation of a Hybrid Dynamic Gold Code-Based Countermeasure Against Side-Channel Attacks [DOI] [Othres link]
• An Efficient Method for Accelerating Kyber and Dilithium Post-Quantum Cryptography [DOI] [Othres link]
• Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC [DOI] [Othres link]
• A Resource-Efficient Multi-core Multi-thread RISC-V-based System-on-Chip [DOI] [Othres link]
• A Trusted Execution Environment RISC-V System on Chip [DOI] [Othres link]
• RISC-V-Based System-on-Chips for IoT Applications [DOI] [Othres link]
• Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding [DOI] [Othres link]
• Compact and Low-Latency FPGA-Based Number Theoretic Transform Architecture for CRYSTALS Kyber Postquantum Cryptography Scheme [DOI] [Othres link]
• RISC-V SoC with NTT-Blackbox for CRYSTALS-Kyber Post-Quantum Cryptography [DOI] [Othres link]
• S-Boxes with Optimal Strict Avalanche Criterion using Chaotic Map [DOI] [Othres link]
• A Trusted Execution Environment RISC-V System-on-Chip Compatible with Transport Layer Security 1.3 [DOI] [Othres link]
• Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems [DOI] [Othres link]
• A Strong 4 × 4 S-Box Using an Enhanced Tent Map [DOI] [Othres link]
• An Efficient Hiding Countermeasure with Xilinx MMCM Primitive in Spread Mode [DOI] [Othres link]
• A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology [DOI] [Othres link]
• A High-Performance Non-Indexed Text Search System [DOI]
• A Novel ECG Signal Quality Index Method Based on Skewness-MODWT Analysis [DOI] [Othres link]
• Construction of Robust Lightweight S-Boxes Using Enhanced Logistic and Enhanced Sine Maps [DOI] [Othres link]
• Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications [DOI]
• A Multimode SHA-3 Accelerator Based on RISC-V System [DOI] [Othres link]
• Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes [DOI] [Othres link]
• High-Speed NTT Accelerator for CRYSTAL-Kyber and CRYSTAL-Dilithium. [DOI] [DBLP] [Othres link]
• FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V [DOI] [Othres link]
• Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks [DOI] [Othres link]
• Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm. [DOI] [DBLP] [Othres link]
• An Efficient Cryptographic Accelerators for IoT System Based on Elliptic Curve Digital Signature [DOI] [Othres link]
• The Efficiency of High-performance SHA-3 Accelerator on the System Level [DOI] [Othres link]
• A High-Speed Barret-Based Modular Multiplication with Bit-Correction for the CRYSTAL-KYBER Cryptosystem [DOI] [Othres link]
• A High-Performance Pipelined FPGA-SoC Implementation of SHA3-512 for Single and Multiple Message Blocks [DOI] [Othres link]
• Optimizing ECC Implementations Based on SoC-FPGA with Hardware Scheduling and Full Pipeline Multiplier for IoT Platforms [DOI] [Othres link]
• A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography [DOI] [Othres link]
• A Survey of Post-Quantum Cryptography: Start of a New Race [DOI] [Othres link]
• Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks [DOI] [Othres link]
• In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology [DOI] [Othres link]
• Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC [DOI] [Othres link]
• A Cross-process Spectre Attack via Cache on RISC-V Processor with Trusted Execution Environment [DOI] [DBLP] [Othres link]
• Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor [DOI]
• A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore [DOI] [Othres link]
• A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators [DOI] [Othres link]
• A Unified PUF and Crypto Core Exploiting the Metastability in Latches [DOI]
• A System-on-Chip for IoT Applications with 16-bit Tiny Processor [DOI]
• High-speed FPGA-based Design and Implementation of Text Search Processor [DOI]
• ChaCha20–Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3 [DOI]
• High-performance Multi-function HMAC-SHA2 FPGA Implementation [DOI]
• Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA [DOI]
• Spectre Attack Detection with Neutral Network on RISC-V Processor [DOI]
• A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse [DOI]
• Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling [DOI]
• Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications [DOI]
• A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor [DOI]
• Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure [DOI]
• A Power-efficient Implementation of SHA-256 Hash Function for Embedded Applications [DOI]
• A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications [DOI]
• ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3 [DOI]
• A Proposal for Enhancing Training Speed in Deep Learning Models Based on Memory Activity Survey [DOI]
• A Trigonometric Hardware Acceleration in 32-bit RISC-V Microcontroller with Custom Instruction [DOI]
• A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip [DOI]
• System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture [DOI]
• A Fully Digital True Random Number Generator with Entropy Source Based in Frequency Collapse [DOI]
• A Sub-μW Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-On-Thin-Box (SOTB) for IoT Applications [DOI]
• Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks [DOI]
• Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processor [DOI]
• Low-power High-performance 32-bit RISC-V Microcontroller on 65-nm Silicon-On-Thin-BOX (SOTB) [DOI]
• Quick Boot of Trusted Execution Environment with Hardware Accelerators [DOI]
• A 0.9-V 50-MHz 256-bit 1D-to-2D-based Single/Multi-match Priority Encoder with 0.67-nW Standby Power on 65-nm SOTB CMOS [DOI]
• A Ring Oscillator Using Bootstrap Inverter [DOI]
• A 0.75-V 58-MHz 340-μW SOTB-65nm 32-point DCT Implementation Based on Fixed-rotation Adaptive CORDIC [DOI]
• A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB [DOI]
• Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias [DOI]
• Live Demonstration: Real-time Auto-exposure Histogram Equalization Video-system Using Frequent Items Counter [DOI]
• A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS [DOI]
• A 1.05-V 62-MHz with 0.12-nW Standby Power SOTB-65nm Chip of 32-point DCT Based on Adaptive CORDIC [DOI]
• An Efficient I/O Architecture for RAM-based Content-Addressable Memory on FPGA [DOI]
• A 0.75-V 32-MHz 181-μW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC [DOI]
• Frequent Items Counter Based on Binary Decoders [DOI]
• VLSI Design of Floating-point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations (Invited paper) [DOI]
• VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study [DOI]
• High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC [DOI]
• A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS [DOI]
• Minimum Adder-delay Architecture of 8/16/32-point DCT Based on Fixed-rotation Adaptive CORDIC [DOI]
• A CORDIC-based QR Decomposition for MIMO Signal Detector [DOI]
• An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation [DOI]
• FPGA-based Frequent Items Counting Using Matrix of Equality Comparators [DOI]
• A Floating-point FFT Twiddle Factor Implementation Based on Adaptive Angle Recoding CORDIC [DOI]
• High-performance DCT Architecture Based on Angle Recoding CORDIC and Scale-free Factor [DOI]
• A Hybrid Adaptive CORDIC in 65nm SOTB CMOS Process [DOI]
• An efficient FPGA-based Database Processor for Fast Database Analytics [DOI]
• A Parallel Pipeline CORDIC Based on Adaptive Angle Selection [DOI]
• An FPGA-based Implementation of FastICA for Variable-length 4-channel Signal Separation
• A Low-resource Low-latency Hybrid Adaptive CORDIC in 180-nm CMOS Technology [DOI]
• Design of Co-processor for Real-time HMM-based Text-to-speech on Hardware System Applied to Vietnamese [DOI]
• Low-resource Low-latency Hybrid Adaptive CORDIC with Floating-point Precision [DOI]
• Database Processor (DBP) - A New Search Engine for the Big Data Era
• An FPGA-based Variable-length 4-Channel Separation FastICA Implementation
• A High-speed Unsigned 32-bit Multiplier Based on Booth-encoder and Wallace-tree Modifications [DOI]
• A Proposed Adaptive Image Segmentation Method Based on Local Excitatory Global Inhibitory Region Growing [DOI]
• An FSM-based IP Protection Technique Using Added Watermarked States [DOI]
• A Constraint-based Watermarking Technique Using Schmitt Trigger Insertion at Logic Synthesis Level [DOI]
• A Case Study of Connect6 Game FPGA-based Implementation Using the Multi-turn Prediction Algorithm
• A Real-time Object-recognition System Based on PCNN Algorithm

その他業績

講演・口頭発表等

• A True Random Number Generator on FPGA with Jitter-Sampling by Ring Generator
• A Compact SHA3 Implementation for Post-Quantum Cryptography
• Resource-Efficient 4×4 S-Boxes Using Chaotic Map
• Hardware Implementation of a Hybrid Dynamic Gold Code-Based Countermeasure Against Side-Channel Attacks
• An Efficient Method for Accelerating Kyber and Dilithium Post-Quantum Cryptography
• A Resource-Efficient Multi-core Multi-thread RISC-V-based System-on-Chip
• A Trusted Execution Environment RISC-V System on Chip
• RISC-V-Based System-on-Chips for IoT Applications
• Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding
• RISC-V SoC with NTT-Blackbox for CRYSTALS-Kyber Post-Quantum Cryptography
• S-Boxes with Optimal Strict Avalanche Criterion using Chaotic Map
• Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems
• A Strong 4 × 4 S-Box Using an Enhanced Tent Map
• An Efficient Hiding Countermeasure with Xilinx MMCM Primitive in Spread Mode
• A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology
• FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V
• Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks
• An Efficient Cryptographic Accelerators for IoT System Based on Elliptic Curve Digital Signature
• The Efficiency of High-performance SHA-3 Accelerator on the System Level
• A High-Speed Barret-Based Modular Multiplication with Bit-Correction for the CRYSTAL-KYBER Cryptosystem
• A High-Performance Pipelined FPGA-SoC Implementation of SHA3-512 for Single and Multiple Message Blocks
• Optimizing ECC Implementations Based on SoC-FPGA with Hardware Scheduling and Full Pipeline Multiplier for IoT Platforms
• Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks
• In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology
• A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore
• A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators
• A System-on-Chip for IoT Applications with 16-bit Tiny Processor
• High-speed FPGA-based Design and Implementation of Text Search Processor
• High-performance Multi-function HMAC-SHA2 FPGA Implementation
• Spectre Attack Detection with Neutral Network on RISC-V Processor
• A Power-efficient Implementation of SHA-256 Hash Function for Embedded Applications
• A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications
• ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3
• A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip
• System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture
• Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processor
• A 0.75-V 58-MHz 340-μW SOTB-65nm 32-point DCT Implementation Based on Fixed-rotation Adaptive CORDIC
• A Ring Oscillator Using Bootstrap Inverter
• Live Demonstration: Real-time Auto-exposure Histogram Equalization Video-system Using Frequent Items Counter
• A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS
• A 0.75-V 32-MHz 181-μW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC
• VLSI Design of Floating-point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations (Invited paper)
• VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study
• High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC
• A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS
• FPGA-based Frequent Items Counting Using Matrix of Equality Comparators
• A Floating-point FFT Twiddle Factor Implementation Based on Adaptive Angle Recoding CORDIC
• High-performance DCT Architecture Based on Angle Recoding CORDIC and Scale-free Factor
• A Hybrid Adaptive CORDIC in 65nm SOTB CMOS Process
• An efficient FPGA-based Database Processor for Fast Database Analytics
• A Parallel Pipeline CORDIC Based on Adaptive Angle Selection
• A Low-resource Low-latency Hybrid Adaptive CORDIC in 180-nm CMOS Technology
• Database Processor (DBP) - A New Search Engine for the Big Data Era
• An FPGA-based Variable-length 4-Channel Separation FastICA Implementation
• A High-speed Unsigned 32-bit Multiplier Based on Booth-encoder and Wallace-tree Modifications
• A Proposed Adaptive Image Segmentation Method Based on Local Excitatory Global Inhibitory Region Growing
• An FSM-based IP Protection Technique Using Added Watermarked States
• A Constraint-based Watermarking Technique Using Schmitt Trigger Insertion at Logic Synthesis Level
• A Case Study of Connect6 Game FPGA-based Implementation Using the Multi-turn Prediction Algorithm
• A Real-time Object-recognition System Based on PCNN Algorithm

書籍等出版物

作品等

共同研究・競争的資金等の研究課題

メディア報道

産業財産権

所属学協会

委員歴

担当経験のある科目

社会貢献活動

学術貢献活動