学位

• 工学修士(上智大学)
• 博士（工学）(上智大学)

経歴

学歴

受賞

• 2023 International Conference On Advanced Technologies For Communications Best Paper Award
• The 5th ASEAN-UEC Workshop on Informatics and Engineering若手研究者奨励賞
• The 19th International SoC Conference (ISOCC 2022)の最優秀論文賞
• 2022 International Conference on IC Design and Technologyの学生最優秀論文賞
• The 18th International SoC Conference (ISOCC 2021)のMetaCNI賞
• The International Symposium on Circuits and Systems (ISCAS 2017)の最優秀論文賞
• 第4回International Conference on Communications and Electronics (ICCE2012)の最優秀論文賞

その他

論文

• Efficient Hardware Implementation of the Lightweight CRYSTALS-Kyber [DOI]
• ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications [DOI]
• A True Random Number Generator on FPGA with Jitter-Sampling by Ring Generator [DOI] [Othres link]
• A Compact SHA3 Implementation for Post-Quantum Cryptography [DOI] [Othres link]
• Resource-Efficient 4×4 S-Boxes Using Chaotic Map [DOI] [Othres link]
• Hardware Implementation of a Hybrid Dynamic Gold Code-Based Countermeasure Against Side-Channel Attacks [DOI] [Othres link]
• A Trusted Execution Environment RISC-V System on Chip [DOI] [Othres link]
• RISC-V-Based System-on-Chips for IoT Applications [DOI] [Othres link]
• A Resource-Efficient Multi-core Multi-thread RISC-V-based System-on-Chip [DOI] [Othres link]
• Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding [DOI] [Othres link]
• Compact and Low-Latency FPGA-Based Number Theoretic Transform Architecture for CRYSTALS Kyber Postquantum Cryptography Scheme [DOI] [Othres link]
• A Trusted Execution Environment RISC-V System-on-Chip Compatible with Transport Layer Security 1.3 [DOI] [Othres link]
• A multimode SHA-3 accelerator based on RISC-V system [DOI] [Web of Scientce] [Othres link]
• RISC-V SoC with NTT-Blackbox for CRYSTALS-Kyber Post-Quantum Cryptography [DOI] [Othres link]
• S-Boxes with Optimal Strict Avalanche Criterion using Chaotic Map [DOI] [Othres link]
• Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems [DOI] [Othres link]
• A Strong 4 × 4 S-Box Using an Enhanced Tent Map [DOI] [Othres link]
• An Efficient Hiding Countermeasure with Xilinx MMCM Primitive in Spread Mode [DOI] [Othres link]
• A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology [DOI] [Othres link]
• Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications [DOI] [Othres link]
• A High-Performance Non-Indexed Text Search System [DOI]
• A Novel ECG Signal Quality Index Method Based on Skewness-MODWT Analysis [DOI] [Othres link]
• Construction of Robust Lightweight S-Boxes Using Enhanced Logistic and Enhanced Sine Maps [DOI] [Othres link]
• Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm. [DOI] [DBLP] [Othres link]
• Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes [DOI] [Othres link] [Scopus] [Scopus]
• High-Speed NTT Accelerator for CRYSTAL-Kyber and CRYSTAL-Dilithium. [DOI] [DBLP] [Othres link]
• High-Efficiency Multi-Standard Polynomial Multiplication Accelerator on RISC-V SoC for Post-Quantum Cryptography [DOI]
• Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System [DOI]
• Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC [DOI]
• FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V [DOI] [Othres link]
• Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks [DOI] [Othres link]
• A High-Speed Barret-Based Modular Multiplication with Bit-Correction for the CRYSTAL-KYBER Cryptosystem [DOI] [Othres link]
• A High-Performance Pipelined FPGA-SoC Implementation of SHA3-512 for Single and Multiple Message Blocks [DOI] [Othres link]
• Optimizing ECC Implementations Based on SoC-FPGA with Hardware Scheduling and Full Pipeline Multiplier for IoT Platforms [DOI] [Othres link]
• The Efficiency of High-performance SHA-3 Accelerator on the System Level [DOI] [Othres link]
• An Efficient Cryptographic Accelerators for IoT System Based on Elliptic Curve Digital Signature [DOI] [Scopus] [Scopus]
• A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography [DOI] [Web of Scientce] [Othres link]
• Efficiency System-level SHA-3 Accelerator for IoT [DOI]
• A Survey of Post-Quantum Cryptography: Start of a New Race [DOI] [Othres link]
• Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks [DOI] [Othres link]
• In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology [DOI] [Othres link]
• Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA [DOI] [Othres link]
• A flexible and efficient FPGA-based random forest architecture for IoT applications [DOI]
• Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC [DOI] [Scopus] [Scopus]
• Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor [DOI] [DOI] [DOI] [DOI] [Web of Scientce] [Othres link]
• A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment. [DOI] [DBLP] [Othres link]
• On the performance of non‐profiled side channel attacks based on deep learning techniques [DOI] [Othres link] [Othres link]
• Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process. [DOI] [DBLP] [Othres link]
• A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore [DOI] [Othres link]
• A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators [DOI] [Othres link]
• A Unified PUF and Crypto Core Exploiting the Metastability in Latches [DOI] [Web of Scientce]
• A System-on-Chip for IoT Applications with 16-bit Tiny Processor
• High-speed FPGA-based Design and Implementation of Text Search Processor
• A High-Performance FPGA-Based Feature Engineering Architecture for Intrusion Detection System in SDN Networks [DOI]
• An Efficient Masking Method for AES Using Tower Fields [DOI]
• A Unified NVRAM and TRNG in Standard CMOS Technology [DOI] [Web of Scientce]
• High-performance Multi-function HMAC-SHA2 FPGA Implementation [DOI]
• Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA [DOI]
• ChaCha20–Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3 [DOI] [Web of Scientce]
• Spectre attack detection with Neutral Network on RISC-V processor [DOI] [Web of Scientce] [Othres link]
• Systems on a Chip with 8bits and 32bits Processors in 0.18μm Technology for IoT Applications [DOI]
• Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling [DOI] [Othres link]
• A Robust and Healthy Against PVT Variations TRNG based on Frequency Collapse [DOI] [Othres link]
• Low Complexity Correlation Power Analysis by Combining Power Trace Biasing and Correlation Distribution Techniques [DOI] [Web of Scientce]
• A Combined Blinding-Shuffling Online Template Attacks Countermeasure Based on Randomized Domain Montgomery Multiplication
• An Obstacle Avoidance Two-Wheeled Self-Balancing Robot [DOI] [Web of Scientce] [Othres link]
• Design of a High-speed 8-bit Flash ADC using Double-Tail Comparator on 180nm CMOS Process [DOI]
• A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications [DOI]
• ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3 [DOI]
• A Power-efficient Implementation of SHA-256 Hash Function for Embedded Applications [DOI]
• A Sub-μW Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications [DOI]
• A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction [DOI] [Othres link]
• A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip
• System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture
• A proposal for enhancing training speed in deep learning models based on memory activity survey [DOI] [Othres link]
• Convergence of 5G Technologies, Artificial Intelligence and Cybersecurity of Networked Societies for the Cities of Tomorrow [DOI]
• 極低電圧用チャージポンプ回路 [DOI]
• Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks [DOI] [Othres link]
• A Real-time Cache side-channel attack detection system on RISC-V Out-of-order processor [DOI] [Othres link]
• Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC with Random Dynamic Frequency Scaling Countermeasure [DOI] [Othres link]
• A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse [DOI] [Othres link]
• Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors [DOI]
• Heterogeneous Hardware-assisted Parallel Processing for BWA-MEM DNA Alignment [DOI]
• Low-power High-performance 32-bit RISC-V Microcontroller on 65-nm Silicon-On-Thin-BOX (SOTB) Date of Evaluation [DOI] [Othres link]
• Dynamic Frequency Scaling as a countermeasure against simple power analysis attack in RISC-V processors.
• TEE Boot Procedure with Crypto accelerators in RISC-V Processors
• Experiment on Replication of Side Channel Attack via Cache of RISC-V Berkeley Out-of-Order Machine (BOOM) Implemented on FPGA
• An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder [DOI] [Othres link]
• Quick Boot of Trusted Execution Environment with Hardware Accelerators [DOI] [DBLP] [DBLP]
• High-Performance FPGA-Based BWA-MEM Accelerator
• A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS [DOI] [Othres link]
• Hardware-Assisted High-performance DNA Alignment System [DOI]
• Hardware-assisted High-performance DNA Alignment System
• Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks [DOI] [DOI] [DOI] [Othres link]
• An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters [DOI] [Othres link]
• Hardware trojan detection techniques using side-channel analysis [DOI]
• An efficient hardware implementation of radix-16 montgomery multiplication [DOI]
• A Ring Oscillator Using Bootstrap Inverter [DOI]
• A 0.75-V 58-MHz 340-μW SOTB-65nm 32-point DCT Implementation Based on Fixed-rotation Adaptive CORDIC [DOI]
• Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias [DOI] [Othres link]
• A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB [DOI] [Othres link]
• A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS [DOI]
• Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter [DOI]
• A 1.05-v 62-mhz with 0.12-nw standby power sotb-65 nm chip of 32-point dct based on adaptive cordic [DOI] [Othres link]
• An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA [DOI] [Othres link]
• A 0.75-V 32-MHz 181- W SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC
• Hardware System for Quaternion Neural Network Dedicated to Real-Time Systems
• Low-resource hardware implementation of ECDSA for the Internet of Things
• Frequent items counter based on binary decoders [DOI] [Othres link]
• VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations [DOI]
• VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study [DOI]
• A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications [DOI]
• A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion
• A 219-µW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS
• High-Speed 8/16/32-Point DCT Architecture Using Fixed-Rotation Adaptive CORDIC
• Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands
• Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC [DOI]
• Dependence of Short-Channel Effects on Semiconductor Bandgap in Tunnel Field-Effect Transistors [DOI] [Othres link]
• High-speed Hardware Implementation of 8-bit per Item Frequent Items Counter
• A Low-Power Hybrid Adaptive CORDIC [DOI]
• A high-throughput low-energy Arithmetic Processor [DOI]
• A CORDIC-based QR decomposition for MIMO signal detector [DOI]
• An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation [DOI]
• An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm [DOI]
• A Flexible High-Bandwidth Low-Latency Multi-Port Memory Controller [DOI] [Othres link]
• Design of ultra-low power AES encryption cores with silicon demonstration in SOTB CMOS process [DOI] [Web of Scientce]
• Quadrature Multi-carrier DCSK: A High-efficiency Scheme for Radio Communications
• A low power AES-GCM authenticated encryption core in 65nm SOTB CMOS process [DOI]
• FPGA-based frequent items counting using matrix of equality comparators [DOI]
• Highly parallel bitmap-based regular expression matching for text analytics [DOI]
• A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion [DOI] [Web of Scientce] [Othres link]
• Reliable and Energy-Efficient Transmission on the Internet-of-Video-Things
• FPGA-based Frequent Items Counting Using Matrix of Equality Comparators [DOI] [Othres link]
• A Low Power AES-GCM Authenticated Encryption Core in 65nm SOTB CMOS Process [DOI]
• Low Power Constant gm Rail-to-Rail Opamp only Using Subthreshold Region
• Highly Parallel Bitmap-Based Regular Expression Matching for Text Analytics [DOI] [Othres link]
• A Low-Latency Parallel Pipeline CORDIC [DOI] [Web of Scientce]
• DYNAMIC NODE LABELING SCHEMES FOR XML UPDATES [Web of Scientce]
• A Floating-point FFT Twiddle Factor Implementation Based on Adaptive Angle Recoding CORDIC [DOI] [Web of Scientce]
• A 180-nm CMOS Bitmap-Index-Based Query Processor for Fast Data Analytics [DOI] [Web of Scientce]
• A hybrid adaptive CORDIC in 65nm SOTB CMOS process [DOI]
• An efficient FPGA-based database processor for fast database analytics [DOI]
• An FPGA approach for high-performance multi-match priority encoder [DOI] [Web of Scientce]
• A High-Throughput and Low-Power Design for Bitmap Indexing on 65-nm SOTB CMOS
• An FPGA approach for fast bitmap indexing [DOI] [Web of Scientce]
• A Parallel Pipeline CORDIC based on Adaptive Angle Selection [Web of Scientce]
• A decentralized localization scheme for swarm robotics based on coordinate geometry and distributed gradient descent [DOI] [Web of Scientce]
• An Efficient FPGA-based DataBase Processor for Fast Database Analytics [Web of Scientce]
• A Hybrid Adaptive CORDIC in 65nm SOTB CMOS Process [Web of Scientce]
• High-performance DCT Architecture Based on Angle Recoding CORDIC and Scale-free Factor [Web of Scientce]
• A Bit-Level Matrix Transpose for Bitmap-Index-Based Data Analytics [Web of Scientce]
• A Compact, Ultra-Low Power AES-CCM IP Core for Wireless Body Area Networks [DOI] [Web of Scientce]
• An All-Digital PLL with SAR Frequency Locking System in 65nm SOTB CMOS [DOI] [Web of Scientce]
• A High-Performance Bitmap-Index-Based Query Processor on 65-nm SOTB CMOS Process [DOI] [Web of Scientce]
• An Ultra-Low Power ANTS Encryption Core in 65nm SOTB CMOS Process [DOI] [Web of Scientce]
• A High-Throughput Multi-Match Priority Encoder for Data Retrieval on 65-nm SOTB CMOS Process [DOI] [Web of Scientce]
• DataBase Processor (DBP) - A New Search Engine for the Big Data Era
• An FPGA Implementation of OFDM System for IEEE 802.22 WRAN
• Parallel pipelining configurable multi-port memory controller for multimedia applications [DOI]
• A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode [DOI] [Web of Scientce]
• Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese [DOI] [Web of Scientce]
• Low-resource low-latency hybrid adaptive CORDIC with floating-point precision [DOI] [Web of Scientce]
• An Efficient Multi-port Memory Controller for Multimedia Applications [DOI] [Web of Scientce]
• Parallel Pipelining Configurable Multi-port Memory Controller For Multimedia Applications [Web of Scientce]
• A Reliable Protocol For Multimedia Transmission Over Wireless Sensor Networks [DOI] [Web of Scientce]
• Design of a Low-power Fixed-point 16-bit Digital Signal Processor Using 65nm SOTB Process [DOI] [Web of Scientce]
• SAR: A Self-Adaptive and Reliable Protocol for Wireless Multimedia Sensor Networks [DOI] [Web of Scientce]
• A 400triV 059m. Lowpower CAM-based Pattern Matching System on 65nm SOTB Process [DOI] [Web of Scientce]
• A Low-resource Low-latency Hybrid Adaptive CORDIC in 180-nm CMOS Technology [DOI] [Web of Scientce]
• A 0.9V 200kHz Current-mode Successive Approximation Analog-to-Digital Converter in 0.18μm CMOS Technology
• Designing a High Performance Cryptographic System for Video Applications
• [Invited] Perpetuum-Mobile Sensor Network Systems using a CPU on 65nm SOTB CMOS Technology
• An FPGA-based Multi-port Memory Controller for High Bandwidth Applications
• A Circuit Structure for MOS Only R-2R Ladder DAC Having Higher Linearity
• Point-to-point H.264 Video Streaming over IEEE 802.15.4 with Reed-Solomon Error Correction
• A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode [Web of Scientce]
• A CAM-Based Information Detection Hardware System for Fast Image Matching on FPGA [DOI] [Web of Scientce]
• A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14 mu A Sleep Current using Reverse Body Bias Assisted 65nm SOTB CMOS Technology [Web of Scientce]
• Design of a Parallel CAM-based Multi-Match Search System Using 0.18-mu m CMOS Process [Web of Scientce]
• A 4pA/Gate Sleep Current 65nm SOTB Logic Gates Using On-chip VBB Generator for Energy Harvesting Sensor Network Systems
• A Design of Differential Digital-Controlled Oscillator in a 0.18um CMOS Process
• Point-to-Point Real-time H.264 Video Streaming over IEEE 802.15.4
• A Compact Improved TDES Cryptography Module for Wearable Medical Devices
• Power Reduction Methodologies for High-Speed Flash ADC Using 180 nm CMOS Process
• An ASIC Implementation of 16-bit Fixed-Point Digital Signal Processor
• An ASIC Implementation of 16-Bit Fixed-Point Digital Signal Processor
• Design a Fast CAM-Based Exact Pattern Matching System on FPGA and 0.18 mu m CMOS Process [DOI] [Web of Scientce]
• A fast CAM-based image matching system on FPGA [DOI]
• Low complexity logarithmic and anti-logarithmic converters for hybrid number system processors and DSP applications [DOI]
• A Fast CAM-based Image Matching System on FPGA [Web of Scientce]
• A Fast CAM-based Watermarking Extraction on FPGA [Web of Scientce]
• Design a Fast CAM-based Information Detection System on FPGA and 0.18 mu m ASIC Technology [Web of Scientce]
• A CAM-based Information Detection Hardware System for fast exact pattern matching [DOI]
• An Efficient ASIC Implementation of Logarithm Approximation for HDR Image Processing [Web of Scientce]
• A 44 mu W/10MHz Minimum Power Operation of 50K Logic Gate using 65nm SOTB Devices with Back Gate Control [Web of Scientce]
• An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory [DOI] [Web of Scientce]
• A CAM-based Information Detection Hardware System for fast pattern matching on FPGA
• A Design of 16-bit Pi-Tpe DAC Employing Three-Stage Indirect Feedback Compensation Opamp
• A PCIe-based FFT Implementation for High-speed Spectrum Analysis
• A Design of Three-Stage CMOS Opamp Using Indirect Feedback Compensation Technique
• The New Structure of Time-to-Digital Converter (TDC) - Multi Diagonal Vernier based TDC
• An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer [DOI] [Web of Scientce]
• Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion [DOI] [Web of Scientce]
• Novel Quasi-Symmetrical Approach for Efficient Logarithmic and Anti-logarithmic Converters
• A novel Information Detection Hardware System
• Low-Area, High-Speed Logarithmic and Anti-logarithmic Converters for Digital Signal Processors Based on Hybrid Number System
• Low-Error and Efficient Fixed-Width Squarer for Digital Signal Processing Applications [Web of Scientce]
• A Fully-Parallel Information Detection Hardware System Employing Content Addressable Memory [Web of Scientce]
• Parameter extraction and optimization using Levenberg-Marquardt algorithm [Web of Scientce]
• A Linearity Optimization Method for CMOS R-2R Ladder Network
• A Constant-gm Rail-to-Rail Operational Amplifier with Low-gain Variation and It's Analysis
• An SoPC for Real-Time Motion Detection Using Spatial-Temporal Entropy
• Efficient LUT-based multiplier and squarer for DSP applications
• Implementation of Search-Less Information Detection based on Content Addressable Memory on FPGA
• Parameter Extraction and Optimization using Levenberg-Marquardt and Genetic Algorithm
• An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer [DOI] [Web of Scientce]
• Low error, efficient fixed width squarer using hybrid LUT-based architecture [DOI]
• A Novel Soft-Start Control Circuit for Current-Mode DC-DC Converter
• Improved linear difference method for sine ROM compression in Direct Digital Frequency Synthesizer
• A Low-Power High-PSRR Low-Dropout Regulator With Bulk-Gate Controlled Circuit [DOI] [Web of Scientce]
• 高速ソフトスタート制御回路を用いた電流モードDC-DCコンバータ [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 電流モードDC-DCコンバータ用小型の適応型スロープ補償回路
• A Compact Adaptive Slope Compensation Circuit for Current-Mode DC-DC Converter [Web of Scientce]
• A DC-DC Converter Using A High Speed Soft-Start Control Circuit [Web of Scientce]
• A Wide Frequency Range and Adjustable Duty Cycle CMOS Ring Voltage Controlled Oscillator [Web of Scientce]
• A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator [DOI] [Web of Scientce]
• 低消費電力シリーズレギュレータ用の負荷過渡応答の高速化回路 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• シリーズレギュレータが高速起動可能な突入電流制限回路の構成 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• FPGA implementation of a Direct Digital Synthesizer using pipelined CORDIC-based approach
• A low-power high accuracy over current protection circuit for low dropout regulator [DOI]
• New Design Method of Low Power Over Current Protection Circuit for Low Dropout Regulator [Web of Scientce]
• Improvement of LDO's PSRR Deteriorated By Reducing Power Consumption : Implementation and Experimental Results [Web of Scientce]
• Low Power LDO with Fast Load Transient Response Based on Quick Response Circuit [Web of Scientce]
• 高速かつ低消費電力な全加算器 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 高精度アクティブ分圧回路 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• シリーズレギュレータの低消費電力化による電源電圧のリプル除去率(PSRR)の劣化の改善 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• ボンディングワイヤの抵抗を考慮したシリーズレギュレータの負荷安定のための補正回路 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• Improvement of power supply rejection ratio of LDO deteriorated by reducing power consumption [Web of Scientce]
• コンパクトなハミング重み比較回路 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 最適設計による高速かつ小規模なディジタル比較回路 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 低消費電力シリーズレギュレータ用の過電流保護回路 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• A Compact Hamming Distance Detector
• Rank Order Filter Using Analog Hamming Comparator
• Image Encryption Method Using Chaotic System Having Dynamic Initial Condition
• Solving Large N-Queen Problem with a Maximum Neuron Model by Canceling Diagonal Competition [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• CMOS schmitt trigger circuit with controllable hysteresis using logical threshold voltage control circuit [Web of Scientce]
• An edge extraction method for color image using multiple-valued LoG filter and color space [Web of Scientce]
• Compensated circuit for Low Dropout Regulator having stable load regulation after consideration of bonding wire resistance [Web of Scientce]
• Quick response circuit for low-power LDO voltage regulators to improve load transient response [Web of Scientce]
• マキシマムニューロン及び修正Hill-Climbing項を用いたN-Queen問題の解法 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• Low Power Full Input Range Current-Mode Operational Amplifier Using Level Shifter Technique [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• An effective solving method for N-Queens problem
• A Robust-Fragile Dual Watermarking System Based on Bilateral Filtering
• A 1.2V Current-Mode Operational Amplifier Using Level Shifter Technique
• CPL-Based Low-Power Full Adder
• A Digital Comparator using Analog Operations
• A proposal to solve N-queens problems using maximum neuron model with a modified hill-climbing term [DOI]
• A 1.5V current-mode operational amplifier using level shifter technique [Web of Scientce]
• A proposal to solve N-Queens problems using maximum neuron model with a modified hill-climbing term [Web of Scientce]
• A hardware accelerator for solving the N-Queen problem [Web of Scientce]
• Simple logic threshold conversion circuits [Web of Scientce]
• 低消費電力全加算器 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• A Stochastic Bit-Stream Digital Neuron Using Generalized LFSR and It's Application to Two-Dimensional Binary Classification [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• Low Power Full Adder Cell using XNOR Circuit of Pass Transistor
• A new N-parallel updating method of the Hopfield-type neural network for N-queens problem [Web of Scientce]
• Tolerance on geometrical operation as an attack to watermarked JPEG image [Web of Scientce]
• 並列Generalized-LFSRを用いた自己組み込みテスト [CiNii Research (CiNii Articles)] [CiNii Books]
• Improvement of Robustness on Embedding of BinaryData to JPEG Image
• A stochastic pulse bit-stream with high accurate multiplication [Web of Scientce]
• A Pulse Model Neuron With High Accurate Calculation and It’s Application to Two-dimensional Binary Classification [Web of Scientce]
• Implementation of a Novel CMOS Synapses Circuit [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• A Novel Synapses Circuit and It's Application to a Neural-Based A/D Converter
• 新型CMOSシナプス回路 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• COMSインバータ回路を用いたニューラルバスAD変換回路
• An Appliction of Genetic Algorithm to a Backward Evolution of Cellular Autowata
• Searching a maximum cycle length in pseudo-random numbers generated by cellular automata [Othres link]
• Simple Methods for Secure Communications Using Nonlinear Mapping Function
• Bifurcational Coummunication with Novel Chaotic Transistors Circuit
• Chaotic behavior and synchronization phenomena in a novel chaotic transistors circuit [Web of Scientce]
• Chaotic behavior and synchronization phenomena in a novel chaotic transistors circuit [DOI]
• A simple 6-bit neural-based A/D converter employing only CMOS inverters [Web of Scientce]
• Bifurcational communication with novel chaotic transistors circuits [Web of Scientce]
• Implementation of nonlinear circuits employing MOSIS
• DISCRETE-TIME CELLULAR NEURAL NETWORKS WITH 2 TYPES OF NEURON CIRCUITS FOR IMAGE-CODING AND THEIR VLSI IMPLEMENTATIONS [Web of Scientce]
• Discrete time cellular neural networks with two types of neuron circuits for image coding and their VLSI implementations [Othres link]
• A Simple Chaos Generator and It's Nonlinear Analysis
• CHAOTIC BEHAVIOR IN SIMPLE LOOPED MOS INVERTERS [Web of Scientce]
• Associative dynamics of competitive cellular neural network [Web of Scientce]
• Pulse coded cellular neural network and it's hardware implementation [Web of Scientce]
• A Novel Chaos Generator Employing CMOS Inverfer for Cellular Neural Networks
• Design of Dynamical Image Halftoning Processor
• Binocular Stereo Vision by Silicon Retina
• BIFURCATION AND CHAOS IN CMOS INVERTERS RING OSCILLATOR [Web of Scientce]
• A SIMPLE NEURAL-BASED A/D CONVERTER EMPLOYING CMOS INVERTERS [Web of Scientce]
• Design and Performance of CMOS Analog Fuzzy Chips
• 2-bit Neuron Circuit for Cellular Neural Network
• A HARDWARE ACCELERATOR FOR DESIGN-RULE CHECKING IN A BIT-MAPPING CAD-SYSTEM [Web of Scientce]
• Pipelining System of Discrete Time Cellular Neural Networks for Information Coding and Decoding
• CMOS DIGITAL RETINA CHIP WITH MULTIBIT NEURONS FOR IMAGE-CODING [Web of Scientce]
• CMOSディジタル回路上のニューラル現象を用いたファジィプロセッサ
• ビットマップCADシステムのためのCMOSセルコンパイラ [Web of Scientce]
• 領域アクセスを行なうビットマップメモリバンク [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• A bitmap memory bank which allows block accesses [DOI] [Othres link]

その他業績

• A Parallel Hybrid Adaptive CORDIC in 180 nm CMOS Technology (集積回路) [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 0.18μm CMOS技術を用いた電流モード逐次比較型A/Dコンバータ (コンピュータシステム) -- (学生・若手研究会) [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 集合演算プロセッサー(SOP) : 画像認識への応用(システムLSIの応用とその要素技術,専用プロセッサ,プロセッサ,DSP,画像処理技術,及び一般) [CiNii Research (CiNii Articles)] [CiNii Books]
• バルク制御によるオペアンプの入力同相電圧広域化 (シリコン材料・デバイス) [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• バルク制御によるオペアンプの入力同相電圧広域化 (集積回路) [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• LCDドライバのためのRail-to-Rail電圧バッファ : 低消費電力と高速化に向けて (集積回路) [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 電流モード型DC-DCコンバータ用小型適応型スロープ補償回路 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 高速ソフトスタート制御回路を用いた電流モードDC-DCコンバータ [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 64ビットディジタルコンパレータ [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• 64ビットディジタルコンパレータ [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]
• エレクトロニクス素子と集積の総合理解を目指す教育－研究・教育活性化支援システム教育プロジェクト－
• パラレルGLFSRを用いた自己組み込みテストにおける故障検出率の向上に関する研究 [CiNii Research (CiNii Articles)] [CiNii Books] [Othres link]

講演・口頭発表等

• A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA Sleep Current using Reverse-Body-Bias Assisted 65nm SOTB CMOS Technology
• 超高速なデータ検索を実現するデータベースプロセッサー（ＤＢＰ） ～ メモリ型コンピューティングで情報処理を大きく進化革新 ～
• CMOS R-2Rラダー型D/Aコンバータの線形性向上法
• 論理閾値変換回路を用いたRing-VCOの発振周波数範囲拡大に関す る研究
• 集合演算プロセッサー(SOP) ― 画像認識への応用
• バルク制御によるオペアンプの入力同相電圧広域化
• MOSFETの動作領域の統一によるD/Aコンバータの線形性の向上 サブタイトル（和）
• LCDドライバのためのRail-to-Rail電圧バッファ-低消費電力と高速化に向けて
• 低エラーのLUTによる打切り乗算器の設計
• CMOS R-2Rラダー回路のチャネル幅調整による線形性最適化に関する研究
• 高速応答の低ドロップアウト(LDO)レギュレータに関する研究
• 電流モード型DC-DCコンバータ用小型適応型スロープ補償回路
• 入力電圧及び負荷変動に適応する効率且つシンプルなDC-DCコンバータ
• Wide Swing, Low Gain Error Voltage Buffer with Adaptive Biasing for Improving Slew-rate
• 高速ソフトスタート制御回路を用いた電流モードDC-DCコンバータ
• Inrush Current Limiting Circuit For for Low Dropout Regulator
• 可変相互コンダクタンス,非線形性,可変利得増幅器,演算トランスコンダクタンス
• 64ビットディジタルコンパレータ
• A Simple Differential Voltage Comparator
• 可変閾値のラプラス－ガウスフィルタを用いた多値画像輪郭抽出法
• ニューロンの新準同期更新方法
• カスタムプロセッサによるOgg Vorbisデコーダの実装
• FPGAを用いた大規模集積行列演算回路の実装に関する研究
• 高精度乗算のための確立演算ビットストリム
• パラレルGLFSRを用いた自己組み込みテストにおける故障検出率の向上に関する研究
• 1補数を用いたパラレル乗算器の設計に関する研究
• FPGAを用いたパイプライン化FFTの設計及び実装に関する研究
• ハードウェア設計システム及びシステムの集積化その２
• ハードウェア設計システム及びシステムの集積化その１
• MOSISへのアクセス
• カオティック・トランジスタ回路における同期現象
• カオティック・トランジスタ
• Chaotic Behavior in CMOS Inverters Ring
• カオティック ＣＭＯＳ インバータ
• Chaotic CMOS Inverters
• 濃淡画像を2値化するCMOS網膜チップ
• CMOS Digital Retinal Chip with 1-bit Neurons for Image Coding
• Implementation of Fuzzy Processors on CMOS Digital IC
• 領域アクセスを行うビットマップメモリバンク
• アナログ・ディジタル・バランス回路を用いた逐次比較型Ａ／Ｄコンバータ
• Successive Approximation Analog-to-Digital conversion employing Analog-Digital-Balance Circuit - Part 2
• BITDRC : A Hardware Accelerator for Design-Rule Checking on bit-mapping CAD System
• ビットマップ方式を取り入れたメモリバンク
• CMOSディジタル・マクロセル・コンパイラ
• ビットマップ方式を取り入れたメモリバンク
• 教材としての２ビットマイクロコンピュータ-LSI Dry and Wet Laboratory-
• Bitmap-IV : A Layout system for Manual and Automatic Design
• Successive Approximation Analog-to-Digital conversion Employing Analog-Digital-Balance Circuit - Part 1
• 画像処理用ビットマップメモリバンク
• ビットマップメモリバンクの設計
• ＶＴＬを用いた手書き論理回路図認識システム
• ビットアクセス用ＤＲＡＭコントローラの設計

書籍等出版物

• 「論理回路」（コンピュータサイエンス教科書シリーズ）

作品等

共同研究・競争的資金等の研究課題

メディア報道

産業財産権

• 曖昧さを含む情報の検出機能を備えた半導体及びこの半導体を組み込んだ装置

所属学協会

• 電子情報通信学会
• IEEE

委員歴

担当経験のある科目

社会貢献活動

学術貢献活動